I am a Graduate student at RMIT University with one-year exchange in Melbourne. I have experience as a Functional Verification Trainee at Faraday Technology Corporation. My skill sets are mainly designing Testbench by using UVM, Verilog and System Verilog for IP on SoC, and reporting Coverage based on the requirement of the Test Item. Moreover, I am familiar with simulator and waveform debugging tools such as Verdi, Xcelium. In addition, I am eager to learn and able to break down, explain complicated information to other. Finally, I would describe myself as a very motivated and a reliable person when it comes to work.